1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly relates to a semiconductor memory device in which power consumption is reduced.
2. Description of Related Art
In recent years, the operation voltage of a semiconductor device is gradually lowered in order to reduce its power consumption. At present, a considerably low operation voltage on the order of 1 volt is often used. However, as the operation voltage is lowered, because it is required to lower the threshold voltage in proportion to the decrease of the operation voltage, it causes a problem that the sub-threshold current of the transistor is increased in a non-conductive state.
To deal with such problems, there has been proposed a method for a semiconductor device disclosed in Japanese Patent Application Laid-open No. H11-31385, which has a structure in which a power source line of a circuit area where logic is fixed at a standby time is divided into a main power source line and a sub power source line. That is, in an active state, the main power source line and the sub power source line are short-circuited so that the power is supplied to both of the lines, thus correctly supplying the operation voltage to the circuit area. On the other hand, in a standby state, the main power source line and the sub power source line are disconnected so that no power is supplied to the sub power source line, thus terminating a power supply to a transistor that does not contribute to maintaining fixed logic that is determined beforehand.
As a result, even when a transistor having a low threshold is used, the power consumption is reduced because the sub-threshold current is reduced in the standby state. In addition, because a switching speed of the transistor having a low threshold is high, a high speed operation of a semiconductor device can be achieved in the active state. That is, it is possible to achieve both the high speed operation and the low power consumption in the semiconductor device.
In a case of applying a low power technology using such a sub power source line as described above to a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), the main power source line and the sub power source line can be disconnected in a period during which the circuit area is in the standby state in response to an external command supplied from outside.
However, if the main power source line and the sub source line are merely disconnected during the period during which the circuit area is in the standby state in response to the external command, it only controls whether to enter the entire chip in the standby mode or to enter the entire chip in the active state. That is, it is not possible to control to enter only a part of an internal circuit in the standby state and to disconnect the main power source line and the sub power source line only in the corresponding circuit portion. Therefore, the power consumption cannot be reduced to a satisfactory extent, and a semiconductor memory device that can further reduce the power consumption has been desired.